1. Field of the Invention
The present invention relates to technique of data-write on memory cells for a semiconductor integrated circuit. More particularly, it relates to enhancement of low power consumption, or high-speed operation, and stable operation during data-write operation.
2. Description of Related Art
With the recent progress of computer technology, there has been needed a memory usable for graphic processing purpose such as three dimensional animation pictures wherein address cycle changes irregularly. In other words, high-speed random access performance is required for a memory regardless of data-readout cycle and data-write cycle. However, this kind of high-speed random access performance is not feasible for synchronous type semiconductor memory devices such as dynamic random access memory (referred to as DRAM hereinafter) and synchronous type DRAM (SDRAM, hereinafter) that multiplex row address and column address and input the addresses with different timing.
As a high-speed memory that can realize high-speed cycle time performance of static random access memory (SRAM, hereinafter) while making the most use of high circuit integration design of DRAM and SDRAM, there has been devised a memory that inputs data without multiplexing addresses and determines whether readout cycle or write cycle within a command. Fast Cycle RAM, or FCRAM (Registered Trademark), is a noticeable example of that.
A memory cell section M1000 in FIG. 9 shows the structure of a high-speed memory. For concise description, FIG. 9 shows a part of the memory, or indispensable structural elements thereof. Memory cells Ta, Tb, Tc, and Td are connected to bit lines /BL, /BLM, BL, BLM, respectively. Data stored in the memory cells Ta, Tb, Tc, and Td are readout as stored charges. After redistributed to the respective bit lines BL, /BL, BLM, /BLM, the stored charges are amplified by sense amplifiers SA, and SAM with being coupled as bit line pair BL, /BL and bit line pair BLM, /BLM. The amplified data are delivered to data bus lines DB, and /DB through column switches TN1, TN2, TN3, and TN4, and then, amplified by a read amplifier RA and outputted from an input/output buffer Buf (from Dout). On the contrary, input data Din are amplified by a write amplifier WA through the input/output buffer Buf, and then, stored in memory cells Ta, Tb, Tc, and Td as charges through bit lines BL, /BL and BLM, /BLM from the data bus lines DB, and /DB.
Out of the memory cells Ta, Tb, Tc and Td, selection of memory cells to be connected the bit line pairs BL, /BL and BLM, /BLM is made by an active signal ACT and a precharge signal PRE transmitted from a row control circuit RC that has received a command signal CMD. More specifically, the active signal ACT and the precharge signal PRE make a word decoder WD active/inactive so as to make signal level of word lines WL and WLM high level. Furthermore, a sense amplifier signal circuit SC controls activation signal LE for the sense amplifiers SA and SAM based on the active signal ACT and the precharge signal PRE. Thereby, the sense amplifiers SA and SAM are made active/inactive. Still further, a column control circuit CC outputs a control signal ACL based on a command signal CMD from the row control circuit RC. Then, a column switch signal circuit Cs controls switch signals CL, and CLM, whereby column switches TN1, TN2, TN3 and TN4 are made conductive/nonconductive.
FIG. 10 shows a waveform diagram of readout operation and FIG. 11 shows that of write operation. A command signal CMD activates the row control circuit RC to output an active signal ACT. Owing to the active signal ACT, the word line WL from the word decoder WD is selected. Then, the memory cells Tc and Td are connected to the bit lines BL and BLM, respectively, and stored charges are redistributed to the bit lines BL and BLM. Up to this point, readout operation and write operation are in the same manner.
Firstly, readout operation will be described. Due to redistribution of stored charges, the bit lines BL and /BL both in equalized state begin to have potential differences gradually (this period is named Period {circumflex over (1)}. As to the bit lines BLM, and /BLM, operation is taken in the same manner as the bit lines BL, and /BL. Accordingly, the following explanation will be omitted. The Period {circumflex over (1)}means a period until the potential difference between the bit lines BL and/BL reaches amplification sensitivity of the sense amplifier SA. The potential difference at this point is of about several ten mV. After the Period {circumflex over (1)} terminates, an activation signal LE for the sense amplifier SA is set to high level. Thereby, the sense amplifier SA is driven to amplify the bit lines BL and /BL (this period is named Period {circumflex over (2)}. After the bit lines BL and /BL are amplified, the control signal ACL is set to high level so as to start up a switch signal CL with high level and readout data on the data bus lines DB and /DB (this period is named Period {circumflex over (3)}. Time that the switch signal CL is kept high level is optimized as the time needed to readout data from the bit lines BL and /BL to the data bus lines DB and /DB. It is the column control circuit CC that sets optimum time.
Next, write operation will be described. When the Period {circumflex over (1)} begins and the memory cell Tc is selected on condition that the memory cells Ta and Tc are connected to the bit lines BL and /BL, respectively, a switch signal CL is set to high level. Thereby, the data bus lines DB and /DB are connected to the bit lines BL and /BL, respectively. Then, the write amplifier WA begins write operation. Since this write operation is made with the switch signal CL being set, this period corresponds to the Period {circumflex over (3)} mentioned in the readout operation. Prompt write operation is required because some data must be inversed to obtain write data and also because the potential difference between the bit lines BL and/BL must reach amplification sensitivity of the sense amplifier SA before the Period {circumflex over (2)} begins. Load that the write amplifier WA must drive is significantly large. That is, the write amplifier WA must drive load for both the data bus lines DB, /DB and the bit lines BL, /BL. Driving ability of the write amplifier WA must be designed high enough to quickly finish data-write on the bit lines BL and /BL before the Period {circumflex over (2)} begins. Since setting time of the switch signal CL (Period {circumflex over (3)} is set by the column control circuit CC and length of the setting time is fixed, the Period {circumflex over (2)} sometimes begins before the Period {circumflex over (3)} terminates.
During write operation, the bit lines BLM and /BLM not subject to data-write exercises the above-mentioned readout operation.
During write cycle, the write amplifier WA needs to write data on the bit lines BL, /BL via the data bus lines DB, /DB, respectively, within a period to readout charges stored in cells (corresponding to the Period {circumflex over (1)} in FIG. 11). That is, within such a short time as the Period {circumflex over (1)}, the write amplifier WA must drive the data bus lines DB, /DB and data bit lines BL, /BL up to a predetermined voltage. Accordingly, driving ability of the write amplifier WA must be designed sufficiently high. Owing to this, an area occupied by the write amplifier WA becomes large on a chip and along with that, power consumption becomes high. This can be an obstacle to trend of semiconductor integrated circuit device design such as higher circuit integration and lower power consumption.
Moreover, data written on the bit lines BL, /BL are amplified up to full amplitude by the sense amplifier SA during amplification period for the bit lines (corresponding to the Period {circumflex over (2)}. In the read operation, it is necessary to surely obtain a readout period (corresponding to the Period {circumflex over (1)}. That is, the bit lines BL, /BL are connected to the data bus lines DB, /DB, respectively, and after the data written on the bit lines are amplified, amplified voltage needs time to be readout on the data bus lines DB, /DB. The column control circuit CC sets the readout period. In the write cycle, the Period {circumflex over (3)} begins to exercise write operation during the Period {circumflex over (1)}. Since the column control circuit CC sets length of the Period {circumflex over (3)} fixedly, the latter half of the Period {circumflex over (3)} and the first half of the Period {circumflex over (2)} sometimes overlap each other in the write cycle. Therefore, the sense amplifier SA must drive loads for not only the bit lines BL, /BL but also the data bus lines DB, /DB. Thus, the amount of loads is large for the sense amplifier SA. Due to restriction of access time, the sense amplifier SA must amplify data on the bit lines BL, /BL within a predetermined time. Therefore, in the event that an amount of loads becomes large, potential difference larger than in the readout time must be written on the bit lines BL, /BL during the Period {circumflex over (3)} within the Period {circumflex over (1)}. On the other hand, in the Period {circumflex over (1)}, charges stored in memory cells are redistributed to the bit lines BL, /BL and the sense amplifier SA has not been activated yet at this point. Therefore, potential difference between the bit lines BLM, /BLM is subtle (of about several ten mv) and it is in floating state. Accordingly, sudden potential change may occur to the bit lines BL, /BL which are subject to data-write. As a result, voltage change occurs to the bit lines BLM, /BLM influenced by capacity coupling between adjacent pairs of bit lines /BL and BLM, for example. Moreover, the potential difference between the bit lines BLM and /BLM is subtle. As a result, potential relation between the bit lines BLM and /BLM is inverted due to noise caused by the capacity coupling.
As higher circuit integration and higher speed operation are demanded for a semiconductor integrated circuit device, increase of an area that a write amplifier WA should occupy on a chip so as to secure driving ability and influence of noise onto the bit lines BLM, /BLM become more problematic. Furthermore, the increase of driving ability for a write amplifier WA is an obstacle to lower power consumption demanded along with higher circuit integration design.
The present invention is intended to solve the foregoing prior art deficiency. Its prime object is to provide a semiconductor integrated circuit device capable of fully achieving low power consumption and high-speed operation during data-write time, and stable operation with less occurrence of noises due to write operation. More specifically, in the inventive semiconductor integrated circuit device, data-write operation on memory cells is exercised after taking the following two steps: (1) input voltage that can be amplified on bit lines; and (2) amplify bit line voltage by blocking data input paths toward the bit lines.
In order to achieve the above objective, the semiconductor integrated circuit device based on one aspect of this invention has memory cells and bit lines which are connected to the memory cells and exercise readout/write of data between the memory cells and the bit lines, wherein the device further includes: a write amplifier for inputting the data on the bit lines so as to write the data on the memory cells; a switching section for connecting the write amplifier and the bit lines; a sense amplifier for amplifying voltage inputted on the bit lines; and the sense amplifier is activated on condition that the write amplifier inputs the data on the bit lines to make the switching section nonconductive.
In the inventive semiconductor integrated circuit device, for data-write on the memory cells, the write amplifier firstly inputs data into the bit lines through the switching section and then, the sense amplifier activates and amplifies data voltage inputted in the bit lines with the switching section nonconductive.
FIG. 1 shows the principle of the present invention. A conduction signal for the switching section and an activation signal for the sense amplifier are signals to make logical high-level active state. The conduction signal for the switching section makes the switching section active only while in a high-level period. The activation signal for the sense amplifier makes the sense amplifier active only while in a high-level period. For switching hi-level periods, or switching active periods of the two signals, a time difference T is taken. Accordingly, it never occurs that the sense amplifier becomes active with the switching section remaining conductive. There is structured an operation sequence wherein the sense amplifier becomes active after the switching section becomes nonconductive.
A data-write method of semiconductor integrated circuit device based on the one aspect of this invention comprises: data input process to input the data to be written on the memory cells to the bit lines; separation process to separate the bit lines from input route of the data after the data is inputted to the bit lines; and amplification process to amplify voltage of the data on the bit lines separated from the input route.
Thereby, data inputted in the bit lines through the switching section made conductive by the write amplifier are amplified by the sense amplifier after the switch section is made nonconductive. The data are amplified up to voltage value to be written in the memory cells. That is, data write operation can be conducted by taking the following two-step operation: (1) the write amplifier inputs bit line voltage up to voltage value to be able to amplify the sense amplifier; and (2) after the bit line voltage is inputted, the sense amplifier for amplifying bit line voltage conducts normal data readout operation. Accordingly, voltage value to be inputted by the write amplifier is limited and driving ability of the write amplifier is reduced to a minimum essential. As a result, circuit scale of the write amplifier is made small, its occupation rate on a chip can be made small, and power consumption can be lowered. This contributes to higher circuit integration design of semiconductor integrated circuit device and lower power consumption. In this case, the minimum value of the bit line voltage to be inputted by the write amplifier corresponds to voltage of the sense amplifier at it samplification sensitivity. If this voltage value is set as a minimum essential voltage, driving ability of the write amplifier can be set to a minimum essential. When the write amplifier inputs voltage higher than the minimum essential, the sense amplifier can surely amplify the bit line voltage and write data on the memory cells.
The above and further objects and novel features of the invention will more fully appear from following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are purpose of illustration only and not intended as a definition of the limits of the invention.